了解 HDL Coder 工具箱

HDL Coder Toolbox
官方文档:https://ww2.mathworks.cn/help/hdlcoder/index.html

简介

Generate VHDL and Verilog code for FPGA and ASIC designs

HDL Coder™ generates portable, synthesizable VHDL® and Verilog® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.

HDL Coder provides a workflow advisor that automates the programming of Xilinx®, Microsemi®, and Intel® FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.

可用性

支持的Matlab数据类型、运算符和控制流
支持HDL代码生成的Matlab函数

支持的Simulink模块
可以用hdllib筛选支持的模块

像是FFT、RAM、乘加单元等的接口与Xilinx家一致,容易替换。

仿真

代码生成

代码

优化空间

官方给的例子来看, 有延迟平衡、多时钟域设计、消除多余逻辑、资源共享等。